Wiegand33 (for PRIMION connections) - SmartRelay 3 system
Signal description
A Wiegand interface uses the following standardised signals:
Signal | Meaning | Explanation | SREL.ADV connection | SREL3 ADV connection | SREL AX Classic connection |
|---|---|---|---|---|---|
D0 | Data 0 | F1 ("D0") | O1 | Output 1 | |
D1 | Data 1 | F2 ("D1") | O2 | Output 2 | |
CLS | Card loading signal | Optionally configurable | F3 (“LED/buzzer/input1”) | O3 | Not available |
All outputs are open-drain. A pull-up resistor (1kΩ to 10kΩ type) and the positive power supply (3 VDC to 24 VDC ) must be provided for signal lines.
The signals are “Active low”.
Signal timing
Time | Description | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|
t CLS- | Time between activation of the CLS signal and first data bit | 8 | 10 | 12 | ms |
tdL | Data bit pulse width | 80 | 100 | 120 | µs |
tpI | Time between two bits (idle time) | 800 | 900 | 1000 | µs |
tpP | Signal period (data rate period) | 900 | 1000 | 1100 | µs |
t CLS+ | Time between last data bit and deactivation of the CLS signal | 8 | 10 | 12 | ms |
Data format (Wiegand 33-bit)
This is a modified Wiegand format. It contains the complete 16-bit facility code (or locking system ID).
Bit number | Meaning |
|---|---|
Bits 1 to 16 | Facility code (0 to 65,535). Bit 1 is MSB. |
Bits 17 to 32 | User ID number (0 to 65,535). Bit 17 is MSB. |
Bit 33 | Parity bit (odd) spanning bits 1 to 32. |