Wiegand26 (standard format) - SmartRelay 3 system
Signal description
A Wiegand interface uses the following standardised signals:
Signal | Meaning | Explanation | SREL.ADV connection | SREL3 ADV connection | SREL AX Classic connection |
|---|---|---|---|---|---|
D0 | Data 0 | F1 ("D0") | O1 | Output 1 | |
D1 | Data 1 | F2 ("D1") | O2 | Output 2 | |
CLS | Card loading signal | Optionally configurable | F3 (“LED/buzzer/input1”) | O3 | Not available |
All outputs are open-drain. A pull-up resistor (1kΩ to 10kΩ type) and the positive power supply (3 VDC to 24 VDC ) must be provided for signal lines.
The signals are “Active low”.
Signal timing
Time | Description | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|
t CLS- | Time between activation of the CLS signal and first data bit | 8 | 10 | 12 | ms |
tdL | Data bit pulse width | 80 | 100 | 120 | µs |
tpI | Time between two bits (idle time) | 800 | 900 | 1000 | µs |
tpP | Signal period (data rate period) | 900 | 1000 | 1100 | µs |
t CLS+ | Time between last data bit and deactivation of the CLS signal | 8 | 10 | 12 | ms |
Data format (Wiegand 26-bit)
This is the standard Wiegand interface. The facility code is shortened to 8 bits.
Bit number | Meaning |
|---|---|
Bit 1 | Parity bit (even) spanning bits 2 to 13 |
Bits 2 to 9 | Facility code (0 to 255). Bit 2 is MSB. |
Bits 10 to 25 | User ID number (0 to 65,535). Bit 10 is MSB. |
Bit 26 | Parity bit (odd) spanning bits 14 to 25. |